This application claims the priority benefit of Taiwan application serial no. 88120701, filed Nov. 26, 1999.
1. Field of the Invention
The invention relates in general to a data accessing system and an method thereof, and more particularly to a data accessing system with an access request pipeline and an access method thereof.
2. Description of the Related Art
In a conventional PCI system, there is a process known as Snoop which checks whether the CPU cache contains data needed by a PCI device through a PCI controller device as the PCI device has to fetch the data from the memory. When the CPU cache contains the data, the data are fetched by the PCI controller device from the CPU cache and provided to the PCI device. When the CPU cache does not contain the data, the data are fetched by the PCI controller device from the memory and provided to the PCI device.
No matter what the data source is, the PCI controller device does not send out a request signal for requesting the next data until the previous data are returned back. That is, when the PCI devices request data continuously, or even at the same time, the PCI controller device must send out the request signal for the first PCI device and fetch a first data corresponding to this request signal. Another procedure is proceeded by the PCI controller device for a second PCI device after the first data is returned to the first PCI device. The PCI controller device then satisfies the read requests from all of the PCI devices one by one with the procedure described above.
Reference is made to FIG. 1, which is a timing chart showing a procedure of a computer system while read requests are processed by using prior art. In FIG. 1, the signal PMADS is asserted to a high level when a PCI master device issues a request. The signal PMRDY is asserted to a high level when the PCI master device is ready to access data. The starting addresses and data are put on the AD signal. The FRAME signal is asserted to a low level to indicate beginning of a transaction, and is deasserted to a high level in 1 clock cycle before the end of transaction. The signal IRDY is asserted to a low level by an initiator (for example, the PCI master device) to indicate that the initiator is ready to accept data. The signal TRDY is asserted to a low level by a target device (for example, the memory module) to indicate that the target device is ready to transmit data. The signal DEVSEL selects a device to be the target device in this transaction. During cycle CLK 4, a read request is issued by the PCI master device, that is, the first pulse on the signal PMADS. The first pulse on the data line AD includes starting addresses of data requested by the PCI master device. At the same time, the level of the signal line FRAME is asserted to indicate that the transaction begins. Thereafter, a signal on a data line PMADS is issued during cycle CLK 5. The level of the signal line PMRDY is asserted during cycle CLK 12 to indicate that the requested data have begun to be transmitted to it. The level of a signal line TRDY is asserted to indicate that the target device is ready to transmit the requested data. Therefore, the PCI master device begins to fetch the requested data from the buffer in the PCI controller device during cycle CLK 13.
Thereafter, the level of the signal line PMRDY is deasserted during cycle CLK 16 to indicate that the transmission of the requested data to the buffer is end, and the requested data are now saved in the buffer. The level of the signal line TRDY is deasserted during cycle CLK 17 to indicate that the target device is not ready to transmit data. For a signal line FRAME being kept in a low level, it means that the PCI master device requests more data. Because of this, another read request is issued during cycle CLK 17. The read request is proceeded in the same procedure as described above, and more requested data are transmitted to the buffer during cycle CLK 24. Thereafter, the PCI master device begins to fetch the requested data from the buffer during cycle CLK 25. When the level of the signal line FRAME is deasserted during cycle CLK 28, it indicates that the data requirement of the PCI master device is fulfilled and the current reading process is finished as well.
From the above discussion, it is understood that there are actually some drawbacks within the PCI data reading operation in the prior art. One of the drawbacks in the prior art is that another read request cannot be issued until all of the previously requested data are transmitted to the buffer of the PCI controller device. As shown in FIG. 1, because the level of the signal line PMRDY is deasserted to indicate that the transaction of the previously requested data is completed during cycle CLK 16, the next read request can be issued by way of the data line PMADS during cycle CLK 17. Therefore, for processing any read request of the PCI master device, there is a latency time in the prior art mentioned above. In FIG. 1, the latency time exists between the cycle CLK 5 and the cycle CLK 12 or exists between the cycle CLK 17 and the cycle CLK 24.
The drawback of the latency time in reading operation results in a low efficiency in the PCI system. Moreover, when the drawback of the limitation of data amount in any reading operation is further considered, the negative effect in efficiency is more serious.
Accordingly, there are at least two drawbacks in the prior art as listed below:
1. The limitation of data transmitted in each reading operation results in dividing the read request of the PCI master device into parts; that is, only after some reading operations can the PCI master device obtain all the data.
2. When processing any read request from the PCI master device, there is a latency time when using the prior art.
The present invention provides a PCI data reading system with read request pipeline, which is adapted to a computer system including a PCI master device, a PCI control device, and a memory module. The PCI master device issues a first read request, and the PCI control device converts the first read request to a second read request divided into a first part and a second part. Each part of the second request requests one line data, i.e 64 bits data. The memory module stores data requested by the PCI master device. Moreover, there is no latency time between data for the first part and the second part returned from the memory module. In one embodiment of the present invention, the PCI control device further includes a read request buffer and a data buffer. The read request buffer stores the second read request, and the second read request is transmitted by the PCI control device with the read request pipeline. The data buffer includes a plurality of data fields, wherein one of the data fields is designated to the PCI master device when the first read request is issued. When data are sent back from the memory module, they are stored in the designated data field.
The present invention also provides a method of using a PCI data accessing system with request pipeline, which is adapted to a computer system including a PCI master device and a PCI control device. The method converts a first request of the PCI master device into a second request including the first request. Then, the present invention stores the second read request. Thereafter, the second request is issued with a pipeline. Finally, data corresponding to the second request is returned and stored. Data are transmitted to the PCI master device while the PCI master device issues the first request again.
From the above discussion, it can be seen that: by using a data buffer with proper capacity, the present invention prefetches data requested by a PCI master device, and therefore reduces the read request frequency of the PCI master device. Moreover, by using a read request buffer, the present invention gathers up read requests of all PCI master device, and issues these read requests with a pipeline. Therefore, the occurrence of latency time is greatly reduced, and the efficiency of the PCI system is greatly increased.